Verilog

Verilog Q: Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run): reg clk; reg a; always #10 clk = ~clk; (1) always @(clk) a = #5 clk; (2) always @(clk) a = #10 clk; (3) always @(clk) a = #15 clk; Now, change a to wire, and draw for: (4) assign #5 a = clk; (5) assign #10 a = clk; (6) assign #15 a = clk; Since the #delay cancels future events when it activates, any delay over the actual 1/2 period time of the clk flatlines… More information...

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