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VLSI Interview Questions with Answers.All the VLSI interview questions and answers asked in all the major IT companies (VERILOG, DIGITAL, PERL, C, STATIC TIMING ANALYSIS, etc) you were…

User:	Saurabh Dayal
Tags:	hardware, digital, c, questions, answers, perl, interview, question, vlsi, ques, sta, static timing analysis, verilog, very large scale integration

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Static Timing Analysis

Static Timing Analysis (STA) Q: What are the types of Timing Verification A: 1. Dynamic timing: The design is simulated in full timing mode. Not all possibilities tested as it is dependent on the input test vectors. Simulations in full timing mode are slow and require a lot of memory.… Read more

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Verilog

Verilog Q: Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run): reg clk; reg a; always #10 clk = ~clk; (1) always @(clk) a = #5 clk; (2) always @(clk) a = #10 clk; (3) always @(clk) a = #15 clk; Now, change a to wire, and draw… Read more

Perl

Perl Q: Write the code for finding the factorial of a passed integer. Use a recursive subroutine. A: // BEGIN PERL SNIPET sub factorial { my $y = shift; if ( $y > 1 ) { return $y * &factorial( $y - 1 ); } else { return 1; } } // END PERL SNIPET Q: Given $a = "5,-3,7,0,-5,12"; Write… Read more

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About Us

About Us This page should contain detailed information about this web project, about your business, products and services, that you are offering. Focus on your qualities, describe the history of your company, cerificates and awards. You can highlight important information or announcements in text like… Read more

Most commonly asked question in VLSI Interviews from all the…

Part1

Part1 Following are contains questions in VERILOG, DIGITAL, PERL, STATIC TIMING ANALYSIS, C : Q: Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run): reg clk; reg a; always #10 clk = ~clk; (1) always @(clk) a = #5 clk; (2) always @(… Read more

Perl

VLSI Interview Questions

All interview questions in: VERILOG ( Blocking, Non Blocking, Tasks, Functions,...) DIGITAL (Flip Flops, Counters,...) PERL (swapping, pattern searching,...) STATIC TIMING ANALYSIS (metastability, setup, hold time,...) C (palindrome, factorial, ...) And many other VLSI interview questions......... So… Read more

Digital

Digital Q: Guys this is the basic question asked most freqently. Design all the basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer. A: Using 2:1 Mux, (2 inputs (I0,I1) , 1 output and a select line) (a) NOT Give the input A at the select line and connect I0 to 1 & I1 to 0. So if A… Read more

C

C Q: Write the code to sort an array of integers. A: /* BEGIN C SNIPET */ void bubblesort (int x[ ], int lim) { int i, j, temp; for (i = 0; i < lim; i+) { for (j = 0; j < lim-1-i; j+) { if (x[j] > x[j+1]) { temp = x[j]; x[j] = x[j+1]; x[j+1] = temp; } /* end if */ } /* end for j */ } /* end… Read more

a

BDV-211609-BDV… Read more

Basic Electronics

Basic Electronics Q: What is Noise Margin? Explain the procedure to determine Noise Margin. A: The minimum amount of noise that can be allowed on the input stage for which the output will not be effected. Q: What happens to delay if you increase load capacitance? A: delay increases. Q: What happens… Read more